1. Field of the Invention
The present invention relates to a charge pumping circuit, and a PLL circuit comprising a charge pumping circuit.
2. Description of the Background Art
FIG. 12 is an explanatory diagram showing the circuit structure of a PLL circuit. As shown in FIG. 12, the PLL circuit is formed by a digital phase comparator 21, a charge pumping circuit 22, a low-pass filter 23, and a voltage controlled oscillator 24.
The digital phase comparator 21 receives input signals SA and SB, brings up and down signals UP and DOWN into active and inactive states respectively on the basis of phase difference between the input signals SA and SB, and outputs the same to the charge pumping circuit 22.
The charge pumping circuit 22 is formed by constant current sources 31 and 32 and switching means 33 and 34, so that the switching means 33, the constant current sources 31 and 32 and the switching means 34 are interposed between a power source VDD and the ground level. The switching means 33 is turned on when the up signal UP is in an active state, for supplying a constant current I0 to a node N1, which is an output part, from the constant current source 31. On the other hand, the switching means 34 is turned on when the down signal DOWN is in an active state, to extract the constant current I0 from the node N I by the constant current source 32.
FIG. 13 is a graph showing exemplary operations of the charge pumping circuit 22 based on the input signals SA and SB. as shown in FIG. 13, the down signal DOWN enters an active state so that the constant current I0 is extracted from the node N1 (-I0) in a period T1 when rise of the input signal SB leads that of the input signal SA, while the up signal UP enters an active state to supply the constant current I0 to the node N1 (+I0) in a period T2 when rise of the input signal SB lags that of the input signal SA.
The low-pass filter 23, having capacitors 35 and 36 and a resistance 37, smooths a voltage which is obtained from the node N1 of the charge pumping circuit 22 and outputs a control voltage SV to the voltage controlled oscillator (VCO) 24.
The voltage controlled oscillator 24 outputs the input signal SB at a frequency which is proportional to the control voltage SV.
In the PLL circuit having the aforementioned structure, the up signal UP of an active state is outputted from the digital phase comparator 21 to increase the control voltage SV thereby increasing the frequency of the input signal SB when the phase of the input signal SB lags that of the input signal SA, while the down signal DOWN of an active state is outputted from the digital phase comparator 21 to reduce the control voltage SV thereby reducing the frequency of the input signal SB when the phase of the input signal SB leads that of the input signal SA. Consequently, the PLL circuit acts to remove the phase difference between the input signals SA and SB, whereby the input signal SB which is in phase with the input signal SA is finally obtained.
FIG. 14 is a circuit diagram showing a concrete internal structure of the charge pumping circuit 22. As shown in FIG. 14, PNP bipolar transistors T51 and T52 have bases which are connected in common, to form a current mirror circuit. The PNP bipolar transistor T51 has an emitter which is connected to a power source VDD through a resistance R51, and a base and a collector which are connected in common. On the other hand, the PNP bipolar transistor T52 has an emitter which is connected to the power source VDD through a resistance R52, and a collector which is connected to an output terminal 50.
NPN bipolar transistors T53 and T54, forming a differential pair, have bases which receive a down signal DOWN and an inverted down signal/DOWN respectively. Collectors of the NPN bipolar transistors T53 and T54 are connected to the output terminal 50 and the power source VDD respectively. Emitters of the NPN bipolar transistors T53 and T54 are connected in common.
Further, NPN bipolar transistors T55 and T56, forming a differential pair, have bases which receive an up signal UP and an inverted up signal/UP respectively. Collectors of the NPN bipolar transistors T55 and T56 are connected to the power source VDD and the output terminal 50 respectively. Emitters of the NPN bipolar transistors T55 and T56 are connected in common.
Bases of NPN bipolar transistors T58, T59 and T60 are connected in common to that of an NPN bipolar transistor T57 having a common base and a common collector, whereby the NPN bipolar transistors T58, T59 and T60 are current mirror-connected to the NPN bipolar transistor T57.
The collector of the NPN bipolar transistor T57 is connected to the power source VDD through a constant current source 10, and its emitter is grounded through a resistance R53. The NPN bipolar transistor T58 has a collector which is connected to the collector (base) of the NPN bipolar transistor T51, and an emitter which is grounded through a resistance R54. The NPN bipolar transistor T59 has a collector which is connected to the emitters of the NPN bipolar transistors T53 and T54, and an emitter which is grounded through a resistance R55. The NPN bipolar transistor T60 has a collector which is connected to the emitters of the NPN bipolar transistors T55 and T56, and an emitter which is grounded through a resistance R56.
The PNP bipolar transistors T51 and T52 are identical in transistor size to each other, while the NPN bipolar transistors T53 to T60 are also identical in transistor size to each other.
In the charge pumping circuit 22 having the aforementioned structure, the NPN bipolar transistors T58, T59 and T60 are current mirror-connected to the NPN bipolar transistor T57, whereby collector currents I52, I59 and I60 of the PNP bipolar transistor T52 and the NPN bipolar transistors T59 and T60 are equal in amount to the constant current I0 of the constant current source 10.
When the input signal SB leads the input signal SA in the period T1 shown in FIG. 13 in the aforementioned structure, the up signal UP of the digital phase comparator 21 enters an inactive state (low level: ground level) while the down signal DOWN enters an active state (high level: power source VDD level).
At this time, the NPN bipolar transistors T53 and T54 are turned on and off respectively, while the NPN bipolar transistors T55 and T56 are turned off and on respectively. Thus, the collector current I52 is supplied to the output terminal 50, while the collector currents I59 and I60 are extracted through the NPN bipolar transistors T53 and T56 which are in ON states, whereby I0-2.multidot.I0=-I0 and the constant current I0 is extracted from the output terminal 50.
When the input signal SB lags the input signal SA in the period T2 shown in FIG. 13, on the other hand, the up signal UP of the digital phase comparator 21 enters an active state while the down signal DOWN enters an inactive state.
At this time, the NPN bipolar transistors T53 and T54 are turned off and on respectively, while the NPN bipolar transistors T55 and T56 are turned on and off respectively. Thus, only the collector current I52 is supplied to the output terminal 50, whereby the constant current I0 is supplied to the output terminal 50.
Thus, the charge pumping circuit 22 carries out a sink operation (extraction) and a source operation (supply) of the constant current I0 on the output terminal 50 on the basis of the up and down signals UP and DOWN of the digital phase comparator 21.
In this case, the voltage range of an output voltage V50 which is obtained from the output terminal 50 is decided as follows: EQU VDD-3VBE-2.DELTA.V (I)
where VBE represents the base-to-emitter voltage of the bipolar transistor (T52, T53 (T56), T59 (T60)), and , .DELTA.V represents the amount of a voltage drop caused by the resistance (R52, R55 (R56)) which is connected to the emitter of the bipolar transistor.
Thus, the voltage range for the output voltage V50 of the charge pumping circuit 22 is limited. Therefore, the voltage range for the control voltage SV of the voltage controlled oscillator 24 is also limited with limitation in the range of the oscillation frequency of the input signal SB, and hence the locking range of the PLL circuit allowing follow-up by the voltage controlled oscillator 24 is unnecessarily limited. This problem is particularly remarkable when the PLL circuit is in pressure reduction or in a low voltage operation.